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| 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74ALVCH162268 12-Bit To 24-Bit Registered Bus Exchanger with 3-State Outputs Product Features * PI74ALVCH162268 is designed for low voltage operation VCC = 2.3V to 3.6V * Hysteresis on all inputs * Typical VOLP (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25C * Typical VOHV (Output VOH Undershoot) < 2.0V at VCC = 3.3V, TA = 25C * B-port outputs have equivalent 26 series resistors, no external resistors are required. * Bus Hold retains last active bus state during 3-state eliminates the need for external pullup resistors * Industrial operation at -40C to +85C * Packages available: - 56-pin 240 mil wide plastic TSSOP (A56) - 56-pin 300 mil wide plastic SSOP (V56) Product Description Pericom Semiconductor's PI74ALVCH series of logic circuits are produced in the Company's advanced 0.5 micron CMOS technology, achieving industry leading speed. This 12-bit to 24-bit registered bus exchanger is designed for 2.3V to 3.6V Vcc operation. The PI74ALVCH162268 is used for applications in which data must be transferred from a narrow high-speed bus to a wide, lower frequency bus. The device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input when the appropriate clock enable (CLKEN) inputs are low. The select (SEL) line is synchronous with CLK and selects 1B or 2B input data for the A outputs. For data transfer in the A-to-B direction, a two stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of these inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B-port. Data flow is controlled by the active-low output enables (OEA, OEB). These control terminals are registered so bus direction changes are synchronous with CLK. The B outputs, which are designed to sink up to 12mA, include equivalent 26 resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible and OE should be tied to VCC through a pullup resistor, the minimum value of the resistor is determined by the current-sinking capability of the driver. Because OE is being routed through a register, the active state of the outputs cannot be determined prior to the arrival of the first clock pulse. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Logic Block Diagram 1 PS8352 11/04/98 Product Pin Description Pin Name OE CLK SEL CLKEN A,1B,2B GND VCC Description Output Enable Input (Active LOW) Clock Select (Active Low) Clock Enable (Active Low) 3-State Outputs Ground Power 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74ALVCH162268 12-Bit To 24-Bit Registered Bus Exchanger with 3-State Outputs Product Pin Configuration OEA CLKEN1B 2B3 GND 2B2 2B1 VCC A1 A2 A3 GND A4 A5 A6 A7 A8 A9 GND A10 A11 A12 VCC 1B1 1B2 GND 1B3 CLKEN2B SEL 1 2 3 4 5 6 7 8 9 10 56 55 54 53 52 51 50 49 48 OEB CLKENA2 2B4 GND 2B5 2B6 VCC 2B7 2B8 2B9 GND 2B10 2B11 2B12 1B12 1B11 1B10 GND 1B9 1B8 1B7 VCC 1B6 1B5 GND 1B4 CLKENA1 CLK Truth Tables(1) Output Enable INPUTS CLK OEA H H L L INPUTS CLKENA1 H L L X X CLKENA2 H L L L L CLK X A X L H L H OUTPUTS OEB H L H L A Z Z Active Active 1B,2B Z Active Z Active OUTPUTS 1B 1B0 (3) 47 11 56-PIN 46 A56 12 45 V56 13 44 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 A to B STORAGE (OEB = L) 2B 2B0 X X L H (3) L(2) H (2) X X B to A STORAGE (OEA = L) INPUTS CLKEN1B CLKEN2B CLK SEL H X L L X X X H L L L L X X H L H H L L 1B X X L H X X 2B X X X X L H Outputs A A0(3) A0(3) L H L H Notes: 1. H = High Signal Level, L = Low Signal Level X = Irrelevant, Z = High Impedance = Transition, Low to High 2. Two CLK edges are needed to propagate data 3. Output level before the indicated steady state input conditions were established. 2 PS8352 11/04/98 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74ALVCH162268 12-Bit To 24-Bit Registered Bus Exchanger with 3-State Outputs Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................................. 65C to +150C Supply Voltage Range, VCC ........................................... 0.5V to 4.6V Input Voltage Range,VI : Except I/O ports (See Note 1): ........................................ 0.5V to 4.6V I/O ports (See Notes 1 and 2) .............................. 0.5V to VCC + 0.5V Output Voltage Range, VO (See Notes 1and 2) .. 0.5V to VCC + 0.5V Input Clamp current, IIK (VI < 0) .............................................. 50mA Output Clamp current, IOK (VO < 0 or VO > VCC) ................... 50mA Continous Output Current, IO (VO = 0 to VCC) ........................ 50mA Continous Current through each VCC or GND ........................ 100mA Maximum Power Dissipation: A package ................................................................... 1W V package ................................................................ 1.4W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Electrical Characteristics (Over the Operating Range, TA = -40C to +85C, VCC = 3.3V 10%) Parame te rs VCC VIH VIL VIN VOUT IOH De s cription Supply Voltage Input HIGH Voltage VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V 0 0 VCC = 2.3V VCC = 2.7V VCC = 3.0V IOL LOW- level Output Current (A Port) VCC = 2.3V VCC = 2.7V VCC = 3.0V IOH HIGH- level Output Current (B Port) VCC = 2.3V VCC = 2.7V VCC = 3.0V IOL LOW- level Output Current (B Port) VCC = 2.3V VCC = 2.7V VCC = 3.0V Te s t Conditions (3) M in. 2.3 1.7 2.0 0.7 0.8 VCC VCC - 12 - 12 - 24 12 12 24 -6 -8 - 12 6 8 12 mA V Typ. M ax. 3.6 Units Input LOW Voltage Input Voltage Output Voltage HIGH- level Output Current (A Port) Notes: 1. The input and output negative-voltage ratings maybe exceeded if the input and outputclamp-current ratings are observed. 2. This value is limited to 4.6V maximum. 3. Unused control inputs must be held HIGH or LOW to prevent them from floating. 3 PS8352 11/04/98 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74ALVCH162268 12-Bit To 24-Bit Registered Bus Exchanger with 3-State Outputs DC Electrical Characteristics-Continued (Over the Operating Range, TA = -40C to +85C, VCC = 3.3V 10% Parame te rs IOH = - 100 IOH = - 6m VOH (A Port) IOH = - 12m IOH = - 24m IOH = - 100 IOH = - 4m VOH (B Port) IOH = - 6m IOH = - 8m IOH = - 12m IOL = 100 IOL = 6m VOL(A Port) IOL = 12m IOL = 24m IOL= 100 IOL = 4m VOL(B Port) IOL = 6m IOL = 8m IOL = 12m II VI = VCC or GND VI = 0.7V VI = 1.7V II (Hold) VI = 0.8V VI = 2.0V VI = 0 to 3.6V(3) IOZ(4) ICC CC CI Control Inputs CIO A or B Ports VO = VCC or GND VI = VCC or GND, IO = 0 One input at VCC - 0.6V, Other inputs at VCC or GND VI = VCC or GND VO = VCC or GND VIL = 0.7V VIL = 0.7V VIL = 0.8V VIL = 0.8V VIL = 0.8V VIL = 0.7V VIL = 0.7V VIL = 0.8V VIL = 0.8V VIH = 1.7V VIH = 1.7V VIH = 2.0V VIH = 2.0V VIH = 2.0V VIH = 1.7V VIH = 1.7V VIH = 2.0V VIH = 2.0V VIH = 2.0V Te s t Conditions VCC(1) Min. toMax. 2.3V 2.3V 2.7V 3.0V 3.0V Min. to Max. 2.3V 2.3V 3.0V 2.7V 3.0V Min. to Max. 2.3V 2.3V 2.7V 3.0V Min. to Max. 2.3V 2.3V 3.0V 2.7V 3.0V 3.6V 2.3V 3.0V 3.6V 3.6V 3.6V 3V to 3.6V 3.3V 3.3V 3.5 9 45 - 45 75 - 75 500 10 40 750 pF M in. VCC - 0.2 2.0 1.7 2.2 2.4 2.0 VCC - 0.2 1.9 1.7 2.4 2.0 2.0 0.2 0.4 0.7 0.4 0.55 0.2 0.4 0.55 0.55 0.6 0.8 5 V Typ.(2) M ax. Units Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25C ambient and maximum loading. 3. Bus hold maximum dynamic current required to switch the input from one state to another 4. For I/O ports, the IOZ includes the input leakage current. 4 PS8352 11/04/98 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74ALVCH162268 12-Bit To 24-Bit Registered Bus Exchanger with 3-State Outputs Timing Requirements over Operating Range Parame te rs fCLOCK tW Clock frequency Pulse duration, CLK high or Low A data before CLK B data before CLK SEL before CLK tSU Setup time CLK ENA1 or CLKENA2 before CLK CLK ENB1 or CLK ENB2 before CLK O E before CLK A data after CLK B data after CLK SEL after CLK tH Hold time CLKENA1 or CLK ENA2 after CLK CLK ENB1 or CLK ENB2 after CLK O E after CLK t/v(1) Input Transition Rise or Fall De s cription VC = 2.5 V 0.2 V C M in. 0 3.3 4.5 0.8 1.4 3.6 3.2 4.2 0 1.3 1 0.1 0.1 0 0 10 M ax. 120 VC = 2.7 V C M in. 0 3.3 4 1.2 1.6 3.4 3 3.9 0 1.2 1 0.1 0 0 0 10 M ax. 125 VC = 3.3 V 0.3 V C M in. 0 3.3 3.4 1 1.3 2.8 2.5 3.2 0.2 1.3 1 0.4 0.5 0.2 0 10 ns/V ns ns M ax. 150 Units Mhz ns Notes: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. Switching Characteristics over Operating Range(1) Parame te rs fMAX tPD tPD tPD tPD tEN tDIS tEN tDIS CLK B A (1B) B (2B) A (SEL) B B A A From (INPUT) To (OUTPUT) VCC = 2.5V 0.2V M in.(2) 120 1.6 1.6 1.6 2.5 2.7 2.8 2 2 6.1 5.8 5.8 7.3 7.2 7.2 6.2 6.5 M ax. VCC = 2.7V M in.(2) 125 5.9 5.4 5.3 6.5 6.8 6.1 5.6 5.4 M ax. VCC = 3.3V 0.3V M in.(2) 150 1.8 1.7 1.8 2.4 2.6 2.5 1.8 2.1 5.4 4.8 4.8 5.8 6.1 5.9 5.1 5 ns M ax.(2) MHz Units Notes: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 5 PS8352 11/04/98 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74ALVCH162268 12-Bit To 24-Bit Registered Bus Exchanger with 3-State Outputs Operating Characteristics, TA= 25C Parame te r CPD Power Dissipation Outputs Enabled Capacitance Outputs Disabled Te s t Conditions CL= 50pF, F = 10 MHz Vcc = 2.5V 0.2V Typical 87 80.5 Vcc = 3.3V 0.3V Typical 120 118 Units pF Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com 6 PS8352 11/04/98 |
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